Summary	"Transplant" architectural register & memory state to RTL
Categories	None
License	GPLv2
Owner(s)	dwaynelee, jsmolens

OpenSPARC T1: Architectural Transplants

The Transplant project provides the capability for simulating portions of real-world, full-system workloads on the OpenSPARC RTL. The key idea is to "transplant" architectural register and memory state from full-system functional simulators such as SAM and Simics to the RTL model. This process allows RTL simulation for workloads such as operating systems and databases that are otherwise too slow to simulate or require resources (e.g., I/O) that are not modeled in RTL.

Transplant Philosophy

The Transplant technique writes a checkpoint of architectural state (architectural user/privileged/hyperprivileged registers, TLB entries) to the OpenSPARC T1 RTL full-chip model and redirects external DRAM requests to a full-system simulator.

The current approach uses a stand alone program to extract architectural register state from a full-system simulator checkpoint. This state is then carefully loaded into the RTL using a small, custom SPARC assembly program. At a well-defined time, the processor then executing from the starting PC of the checkpoint, external memory is switched over to the full-system simulator's image and various hard-to-initialize RTL structures (notably the I- and D- TLBs) are set.

Source code

A drop-in tarball built off the OpenSPARC T1 v1.4 release RTL is available from the CVS link to the left, under "releases".

An overview of installing and running transplant checkpoints is available here.

Implementation Status

The current implementation consists of the following modifications to the OpenSPARC v1.4 release:

• PLI code for interfacing with an external full-system Niagara simulator (currently Simics/Niagara).
• Simics/Niagara module for supplying architectural register and memory state to the RTL model.
• Assembly routines and PLI code to slam architectural register state into an OpenSPARC T1 RTL model, starting from a standard assembly regression test.
• PLI code to intercept memory reads and writes in RTL and reply with correct data from the functional simulator, including ECC bits.
• Serial port UART interception to transfer console I/O requests to the full system simulator host.
• A utility for translating checkpoints from a full-system simulator into assembly code that initializes the RTL model.

The transplant implementation has been tested with a 1-strand checkpoint of Solaris 10 and user applications running on Simics/Niagara 3.0.27. The system has run unmodified user and OS code for several million core clocks and output several lines of text to the system console.

Future tasks

• Updating to OpenSPARC 1.5 release
• Supporting more than one strand (and core).
• Validating coverage of all architectural user, privileged and hyper-privileged registers and TLB entries (start with user-level).
• Support for reading additional functional simulators such as SAM and SAM's checkpoints.
• Detection of external I/O events on the IOB and JBus, transplanting state between the functional simulator and RTL model during these events, and resuming execution in RTL.
• Ability to slam cache tag/data array checkpoints from a microarchitectural simulator (caches/on-chip directory are currently invalidated).

Contact Info

The transplant code is written by Jared Smolens with help from Eric Chung, both graduate students from the Computer Architecture Lab at Carnegie Mellon. Both students are advised by James C. Hoe. This project is an extension of the ProtoFlex project. Please post questions or comments regarding OpenSPARC transplants on the OpenSPARC general discussions forum.